Secure data storage based on physically unclonable functions

ABSTRACT

Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.

CROSS-REFERENCE TO RELATED APPLICATION

This Application is a Divisional under 35 U.S.C. §121 of and claimspriority under 35 U.S.C. §120 to U.S. application Ser. No. 14/515,425,entitled “Secure Data Storage based on Physically Unclonable Functions,”filed on Oct. 15, 2014. The disclosure of U.S. application Ser. No.14/515,425 is incorporated by reference herein in its entirety and forall purposes.

BACKGROUND

Unless otherwise indicated herein, the materials described in thissection are not prior art to the claims in this application and are notadmitted to be prior art by inclusion in this section.

As electronic transactions involving sensitive information such asfinancial and personal information become more prevalent, concerns aboutdata security also increase. To address these concerns, various securitymeasures may be employed. Such security measures may includecryptographic techniques such as symmetric or asymmetric cryptographicalgorithms, as well as physical security techniques that rely ondisordered physical systems for authentication.

SUMMARY

The present disclosure generally describes techniques for secure datastorage based on physically unclonable functions extracted fromnonvolatile memories.

According to some examples, a method is provided to program data on anonvolatile memory using a physically unclonable function. The methodmay include determining, for multiple memory bits on the nonvolatilememory, a program threshold average and a program threshold variation.The method may further include deriving, based on the program thresholdaverage and the program threshold variation, a first bin threshold and asecond bin threshold, and grouping the bits into at least a first groupof bits, a second group, and a third group, based on at least the firstbin threshold and the second bin threshold. The method may furtherinclude determining, based on at least the grouping of the bits, a setof bits to which the data is to be written, and performing a partialprogram of the data to the set of bits based on the program thresholdaverage and the program threshold variation.

According to other examples, an encoding module is provided to programdata on a nonvolatile memory with the knowledge of a physicallyunclonable function. The encoding module may include an interfaceconfigured to couple to multiple memory bits on the nonvolatile memoryand a processor block. The processor block may be configured todetermine, for the multiple memory bits, a program threshold average anda program threshold variation. The processor block may be furtherconfigured to derive, from the program threshold average and the programthreshold variation, a first bin threshold and a second bin threshold,and group the multiple bits into at least a first bit group, a secondbit group, and a third bit group, based on at least the first binthreshold and the second bin threshold. The processor block may befurther configured to determine, based on at least the grouping of thebits and a key mask, a set of bits to which the data is to be written,and performing a partial program of the data to the set of bits based onthe program threshold average and the program threshold variation.

According to further examples, a method is provided to read data from anonvolatile memory with the knowledge of a physically unclonablefunction. The method may include applying at least one partial programpulse to at least one bit in multiple memory bits in the nonvolatilememory based on a program threshold average, a program thresholdvariation, and/or a bit group characterization associated with the atleast one bit. The method may further include reading a resulting stateof the multiple memory bits and deriving a final data based on theresulting state and another data value.

According to yet further examples, a decoding module is provided withadditional partial program cycles in order to retrieve the correct data.The decoding module may include an interface configured to couple tomultiple memory bits in the nonvolatile memory and a processor block.The processor block may be configured to apply at least one programpulse to one or more bits in the multiple memory bits based on a programthreshold average, a program threshold variation, and/or a bit groupcharacterization associated with the bit(s), where the program thresholdmay represent a number of partial program pulses to modify a bit in thememory bits from a first value to a second value. The processor blockmay be further configured to read a resulting state of the multiplememory bits and derive a final data based on the resulting state andanother data value.

The foregoing summary is illustrative only and is not intended to be inany way limiting. In addition to the illustrative aspects, embodiments,and features described above, further aspects, embodiments, and featureswill become apparent by reference to the drawings and the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features of this disclosure will become morefully apparent from the following description and appended claims, takenin conjunction with the accompanying drawings. Understanding that thesedrawings depict only several embodiments in accordance with thedisclosure and are, therefore, not to be considered limiting of itsscope, the disclosure will be described with additional specificity anddetail through use of the accompanying drawings, in which:

FIG. 1 is a system diagram illustrating an example nonvolatile memorydevice containing physically unclonable functions (PUFs);

FIG. 2 is an illustration of the physically unclonable programcharacteristics of a memory device, which are represented by the numberof partial program cycles to flip the state of the bit to the senseamplifier module;

FIG. 3 is an illustration of a first example of data being written toand recovered from a memory device with the knowledge of physicallyunclonable functions;

FIG. 4 is an illustration of a second example of data being written toand recovered from a memory device by use of physically unclonablefunctions;

FIG. 5 is an illustration of a third example of data being written toand recovered from a memory device by use of physically unclonablefunctions;

FIG. 6 is an illustration of a first example process for programming andrecovering data on a memory device using partial program cycles as PUFs;

FIG. 7 is an illustration of a second example process for programmingand recovering data on a memory device using partial program cycles asPUFs;

FIG. 8 is an illustration of a general purpose computing device, whichmay be used to provide secure data storage based on physicallyunclonable functions;

FIG. 9 is a flow diagram illustrating an example method for providingsecure data storage based on physically unclonable functions that may beperformed by a computing device such as the computing device in FIG. 8;and

FIG. 10 is an illustration of a block diagram of an example computerprogram product, all arranged in accordance with at least someembodiments described herein.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof. In the drawings,similar symbols typically identify similar components, unless contextdictates otherwise. The illustrative embodiments described in thedetailed description, drawings, and claims are not meant to be limiting.Other embodiments may be utilized, and other changes may be made,without departing from the spirit or scope of the subject matterpresented herein. It will be readily understood that the aspects of thepresent disclosure, as generally described herein, and illustrated inthe Figures, can be arranged, substituted, combined, separated, anddesigned in a wide variety of different configurations, all of which areexplicitly contemplated herein.

This disclosure is generally drawn, inter alia, to methods, apparatus,systems, devices, and/or computer program products related to securedata storage based on physically unclonable functions (PUFs).

Briefly stated, technologies are generally described for partialprogramming of memory having physically unclonable functions for securedata storage. In some examples, a sender that wishes to securely senddata to a recipient using a physical memory may measure a programthreshold average and a program threshold variation for bits in thememory and group the bits into different bins based on the measuredaverage and variation. The sender may partially program the data to aset of bits selected from one or more of the bins by applying partialprogram pulses to the bits based on the program threshold average andthe program threshold variation. The sender may then provide thepartially-programmed memory to the recipient. The recipient may thenpartially program the received memory based on the program thresholdaverage and the program threshold variation to recover the programmeddata.

FIG. 1 is a system diagram illustrating an example memory device havingphysically unclonable functions (PUFs), arranged in accordance with atleast some embodiments described herein.

According to a system diagram 100, a physical memory 102 may include amemory controller 104, a read module 106, a program/erase module 108,and memory cells 110. The memory cells 110 may store one or more binarydata bits per cell, and may be volatile (for example, dynamicrandom-access memory) or nonvolatile (for example, flash or EEPROMmemory). In the latter case, the memory cells 110 may be implementedusing floating gate devices that store data values as charge or chargecarriers. A charge threshold may be used to delineate different datavalues. A memory cell storing more charge than the charge threshold maybe considered to store one value (for example, a binary “1”), whereas amemory cell storing less charge than the charge threshold may beconsidered to store a different value (for example, a binary “0”). Inother embodiments, the charge-to-value correspondence may be reversed(that is, charge less than the threshold corresponds to a binary “1”),and multi-level cells capable of storing multiple bits per cell mayimplement multiple thresholds. The memory cells 110 may be organizedinto one or more words, pages, blocks, or sections of any suitable size.In one embodiment, the memory cells 110 may include an 8-bit word 120that includes memory cells 121-128.

The memory controller 104 may read data from or program data to thememory cells 110 using the read module 106 and the write module 108,respectively. In some embodiments, the memory controller 104 may programdata to the memory cells 110 by using the program module 108 to adjustthe charge stored on one or more memory cells to move above or below thecharge threshold, thereby changing the data values stored on the memorycells. The program module 108 may adjust charge stored on a memory cell,such as the memory cell 121, by applying varying voltage and/or currentvalues to the memory cell. In some embodiments, the program module 108may apply one or more discrete voltage/current pulses, or “programpulses”, to modify charge stored on the memory cell 121. Each programpulse may have a predetermined or dynamically-determined voltage orcurrent value, and may last for a predetermined ordynamically-determined time duration. In some embodiments, a singleprogram pulse may not supply sufficient charge to change the data valuestored on the memory cell 121. Accordingly, the program module 108 mayapply a series of program pulses to the memory cell 121 until enoughcharge has been supplied to change the data value stored on the memorycell 121. The number of program pulses that supplies enough charge tochange the data value stored on a memory cell may be referred to as a“program threshold”.

In some embodiments, the program threshold for a memory cell may varyaccording to the memory cell. For example, if the memory cell 121 isinitially fully uncharged, the program module 108 may apply programpulses (having a particular voltage/current value and time duration)according to a first program threshold to the memory cell 121 to changethe data value stored at the memory cell 121. In contrast, the programmodule 108 may have to apply program pulses (having the samevoltage/current value and time duration) according to a second programthreshold different from the first program threshold to the memory cell122 to change the data value stored at the memory cell 122. The programthreshold associated with a particular memory cell may depend on bitphysical characteristics resulting from the memory manufacturingprocess. For example, the memory manufacturing process, being a physicaland relatively stochastic (or random) process, may inherently result inmemory cells having random variations in defect levels, dopant levels,and dimensions. These variations, while generally stable over time andnot substantially affecting the functionality of the manufactured memorycells, nevertheless may vary the program/erase characteristics of thememory cells. As a result, different bits on a memory may have differentprogram thresholds.

The random variations in memory cell program thresholds may be used as asecurity function. Because the variations originate from the physicalmemory manufacturing process, replication of the variations may bedifficult if not outright impossible. Such variations may be referred toas “physically unclonable functions”, or PUFs. The PUFs associated withvariations in program thresholds may be combined with “partial program”operations. A partial program operation is an operation in which programpulses are applied to a bit, but a single or small number of programpulses are not enough to actually reach the memory cell's programthreshold. For example, if a memory cell's program threshold requires 20such partial program pulses, a partial program operation may involve theapplication of 10 program pulses, 15 program pulses, or any other numberof program pulses less than 20 to the memory cell. In such a case, aread of the memory cell may indicate that the memory cell stores theoriginal, unchanged data value, despite the applied program pulses. As aresult, data may be encoded to the memory cell without being externallyvisible or readable. When data is secured using PUFs and partial programoperations, an attacker would need to actually possess the physicalinstantiation of the PUFs and be able to identify the memory cellsstoring the data in order to be able to retrieve the stored data.

FIG. 2 is an illustration of the physically unclonable programcharacteristics of a memory device, arranged in accordance with at leastsome embodiments described herein.

According to a diagram 200, an 8-bit word 210 (similar to 8-bit word 120in FIG. 1) may include eight memory cells or bits 201-208. The bits201-208 may each be associated with different program thresholds, forexample due to the variations described above. For example, the bit 201may have a program threshold of 20, the bit 202 may have a programthreshold of 15, the bit 203 may have a program threshold of 30, and thebit 204 may have a program threshold of 17. The bit 205 may have aprogram threshold of 18, the bit 206 may have a program threshold of 22,the bit 207 may have a program threshold of 20, and the bit 208 may havea program threshold of 10. The program thresholds associated with eachof the bit 201-208 may be represented by a “program threshold” vector220.

The program thresholds associated with a set of bits such as the bits201-208 may be characterized using a mean (α) and a standard deviation(Δ). For example, based on the example data in the vector 220, the α ofthe write thresholds of the bits 201-208 is 19, and the Δ is 5.78. Insome embodiments, the α and Δ may be further used to group the bits201-208 into a number of bins according to the bits' program threshold,as depicted by bit bin number vector 230. Bits that have programthresholds less than α−Δ (about 13 program pulses according to theexample data in this figure) may be assigned to a first bin (bin 1) andrepresented by a bin map. Only the bit 208 of the bits 201-208 fallsinto bin 1, and accordingly the bin map for bin 1 is “00000001”, wherethe “1” value corresponds to the bit 208 at the end of the 8-bit word210. Bits that have program thresholds greater than α−Δ (about 13program pulses according to this example) but less than α+Δ (about 26program pulses according to this example) may be assigned to a secondbin (bin 2). The bits 201, 202, 204, 205, 206, and 207 fall into bin 2,and accordingly the bin map for bin 1 is “11011110”, where the “1”values correspond to the bits 201, 202, 204, 205, 206, and 207. Bitsthat have program thresholds greater than α+Δ (about 26 write pulsesaccording to this example) may be assigned to a third bin (bin 3). Onlythe bit 203 falls into bin 3, and accordingly the bin map for bin 3 is“00100000”, where the “1” value corresponds to the bit 203 in the thirdposition of the 8-bit word 210. Organizing bits into different binsbased on program thresholds may allow the selection of appropriate bitson which data should be encoded to take advantage of the additionalsecurity provided by the use of PUFs and partial program operations.

FIG. 3 is an illustration of a first example of data being written toand recovered from a memory device having PUFs, arranged in accordancewith at least some embodiments described herein.

A diagram 300 illustrates how a word “00010001” may be written to thebits 201-208 having the program thresholds described in FIG. 2. A sendermay wish to transmit the word “100010001” to a recipient. The sender mayuse a program module such as the program module 108 to partially programthe word “00010001” to the initially-uncharged bits 201-208 by applyingα−Δ or 13 program pulses to the bits 204 and 208 and zero program pulsesto the other bits 201-203 and 205-207. After the program pulses havebeen applied, a diagram 310 depicts the data values of the bits 201-208in the upper row of blocks as well as the number of program pulsesneeded to change the bit data value (referred to as a “pulses-remainingvalue”) in the lower row of blocks. Since the bits 201-203 and 205-207have not had program pulses applied, their data values may remain at “0”and their pulses-remaining values may remain at their original writethresholds. Thirteen (13) program pulses were applied to the bits 204and 208. The bit 204 had a program threshold of 17, and after theapplication of 13 write pulses now may have a pulses-remaining value of4 (17-13=4). Because the number of applied program pulses is not enoughto change the data value of the bit 204, the bit 204 remains at “0”. Thebit 208 had a program threshold of 10, and applying 13 program pulsesmay have been sufficient to change the data value of the bit 208.Accordingly, the data value of the bit 208 may now be “1”, and thepulses-remaining value of the bit 208 may now be 0 (that is, no furtherpulses are needed to change the data value of the bit 208).

Subsequently, the sender may provide the physical memory containing thebits 201-208 to the recipient to which the word “00010001” is to betransmitted. The transfer of the physical memory may ensure that therecipient has access to the physical instantiation of the partialprogram operation of the word “00010001” on the bits 201-208. Therecipient may use a program module similar to the program module 108 toperform a uniform or blind partial program operation on all of the bits201-208 by applying 2Δ or 12 program pulses to each of the bits 201-208,resulting in the subsequent data values and pulses-remaining values ofthe bits 201-208 depicted in a diagram 320. In the diagram 320, thepulses-remaining values of each of the bits 201-208 may be decrementedby 12 from their values in the diagram 310, and if the resultingpulses-remaining value is less than or equal to 0, then thecorresponding bit may change its stored “digital” value. For example,the bit 204 had program pulses applied previously resulting in apulses-remaining value of 4 as shown in the diagram 310. The applicationof 12 program pulses may be enough to reduce the pulses-remaining valueof the bit 204 to less than 0, and as such the data value of the bit 204may change to “1”.

The recipient may then use the program module to perform another uniformor blind partial program operation on all of the bits 201-208 byapplying another 2Δ or 12 program pulses to each of the bits 201-208,and a diagram 330 depicts the subsequent data values andpulses-remaining values of the bits 201-208. In the diagram 330, thepulses-remaining values of each of the bits 201-208 may be decrementedby 12 from their values in the diagram 320, and if the resultingpulses-remaining value is less than or equal to 0, then thecorresponding bit may change its stored “digital” value. As depicted,the bits 201, 202, 205, 206, and 207, all of which are categorized inbin 2, may now switch data values to “1”, whereas the bit 203, which iscategorized in bin 3, may still have a pulses-remaining value of 6 andtherefore may remain at data value “0”.

In some embodiments, after the first blind partial program operation of2Δ program pulses the recipient may be able to retrieve the word“00010001” that was partially written. However, in the diagram 320 itmay be difficult to determine whether (a) whether the bit 208categorized in bin 1 was supposed to store a “0” or a “1”, and (b)whether the bits with “0” values have “0” values because they aresupposed to store “0” values or because they are in bin 3. For thelatter situation, the second blind partial program operation of 2Δ maydistinguish the bits belonging to bin 2 and the bits belonging to bin 3.

FIG. 4 is an illustration of a second example of data being written toand recovered from a memory device having PUFs, arranged in accordancewith at least some embodiments described herein.

A diagram 400, similar to the diagram 300, illustrates how a word“10101010” may be written to the bits 201-208 having the programthresholds described in FIG. 2. A sender may wish to transmit the word“10101010” to a recipient. The sender may use a program module topartially write the word “10101010” to the initially-uncharged bits201-208 by applying α−Δ or 13 program pulses to the bits 201, 203, 205,and 207 (all of which are in bin 2 except for the bit 203) and zeroprogram pulses to the other bits 202, 204, 206, and 208. After theprogram pulses have been applied, a diagram 410 depicts that none of thebits 201-208 may have changed their “digital” values, although thepulses-remaining values associated with all of the bits to which programpulses have been applied have been decremented by 13.

Subsequently, the sender may provide the physical memory containing thebits 201-208 to the recipient. The recipient may then use a programmodule to perform a blind partial program operation on the bits 201-208by applying 2Δ or 12 program pulses to each of the bits 201-208,resulting in the data values and pulses-remaining values depicted in adiagram 420. In the diagram 420, the bits 201, 205, and 207, which hadpartial programs applied previously, may all have changed values to “1”.However, the bit 208, which was not written to previously, also changedvalues, whereas the bit 203, which had partial programs appliedpreviously, may not change values. The program module may then applyanother 2Δ or 12 program pulses to each of the bits 201-208, resultingin the data values and pulses-remaining values depicted in a diagram430. In the diagram 430, all of the bits now may have changed values. Inthis example, the recipient without the PUF knowledge may not be able tofully retrieve the word “10101010” after the first blind partialprogram, both because the bit 203 (in bin 3), which should have stored a“1”, may not have changed value, and the bit 208 (in bin 1), whichshould have stored a “O”, did change value.

FIG. 5 is an illustration of a third example of data being written toand recovered from a memory device having PUFs, arranged in accordancewith at least some embodiments described herein.

A diagram 500, similar to the diagrams 300 and 400, illustrates how aword “11111111” may be written to the bits 201-208 having the programpulses parameters described in FIG. 2. A sender may wish to transmit theword “11111111” to a recipient. The sender may use a program module topartially write the word “1111111” to the bits 201-208 by applying α−Δor 13 program pulses to each of the bits 201-208. As depicted in adiagram 510, after the program pulses have been applied to the bits201-208 the bit 208 (categorized in bin 1) may change value to “1” whilethe other bits 201-207 may not change value, although thepulse-remaining values associated with the bits 201-207 may decrease.

Subsequently, the sender may provide the physical memory containing thebits 201-208 to recipient to which the word “11111111” is to betransmitted. The recipient may then use a program module to perform ablind partial program operation on the bits 201-208 by applying 2Δ or 12program pulses to each of the bits 201-208, resulting in the data valuesand pulses-remaining values depicted in a diagram 520. In the diagram520, all of the bits except for the bit 203 may have changed values. Theprogram module may then apply another 2Δ or 12 program pulses to each ofthe bits 201-208, resulting in the data values and pulses-remainingvalues depicted in a diagram 530. In the diagram 530, all of the bitsnow may have changed their “digital” values. In this example, therecipient without the PUF knowledge may not be able to fully retrievethe word “11111111” after the first blind partial program, because thebit 203 (in bin 3), which should have stored a “1”, may not have changedvalue.

FIG. 6 is an illustration of a first example process 600 for programmingand recovering data on a memory device having PUFs using partialprogramming, arranged in accordance with at least some embodimentsdescribed herein. Process 600 may include one or more operations,functions, or actions as illustrated by one or more of blocks 602-618.Although some of the blocks in process 600 (as well as in any otherprocess/method disclosed herein) are illustrated in a sequential order,these blocks may also be performed in parallel and/or in a differentorder than those described herein. Also, the various blocks may becombined into fewer blocks, divided into additional blocks, and/oreliminated based upon the particular implementation. Additional blocksrepresenting other operations, functions, or actions may be provided.

According to process 600, programming and recovering data on a memorydevice having PUFs using partial programming may begin at block 602(“Sender performs complete erase of page/block”), where a sender whowishes to transmit data to a receiver using a memory device maycompletely erase the portion of the memory device that will store thedata to be transmitted. At block 604 (“Sender measures programthresholds for bits in page/block and assigns to three bins”), which mayfollow block 602, the sender may measure the program thresholds for eachbit in the completely-erased memory portion. In some embodiments, thesender may perform the measurement by using a program module such as theprogram module 108 to apply program pulses to each bit until the datavalue stored at the bit changes. After measuring the program thresholds,the sender may record them and group the bits in the memory portion intothree bins, as described above. In other embodiments, the sender maygroup the bits into more or fewer bins. In some embodiments, only memorythat have α>3Δ may be used if the bit bin maps are not distributed topotential receivers. After measuring the program thresholds, the sendermay again perform a complete erase of the memory portion.

At optional block 606 (“Sender computes data-to-write from intended dataand password-derived code”), which may follow block 604, the sender mayuse a password-derived code to compute the data to be written on thememory. In some embodiments, the sender may compute the data bycombining an intended data with the password-derived code using abitwise AND, XOR or XNOR functions.

At block 608 (“Sender partially programs data to specific bits in middlebin using α−Δ pulses for ‘1’ bits and no pulses on ‘0’ bits”), which mayfollow block 606, the sender may use the program module to apply α−Δprogram pulses to bits in the middle bin (that is, bits with programthresholds between α−Δ and a+A) based on the data to be transmitted tothe recipient. For example, the sender may use a key mask or some othermethod to select the bits in the middle bin onto which the data is to bepartially programmed. The sender may then partially program the selectedbits with the data by applying α−Δ program pulses to bits in theselected bits that are to store “1” values and no pulses to bits in theselected bits that are to store “0” values. Because the selected bitsare in the middle bin, even the bits partially programmed with programpulses may not appear to store “I” values when read without the PUFknowledge. At block 610 (“Sender programs bits in first bin using α−Δpulses and bits in third bin with no pulses”), which may follow block608, the sender may then program bits in the first bin (that is, thebits with program thresholds less than α−Δ) with α−Δ program pulses,assuring that those bits will appear to store “1” values when read. Thesender may not program or partially program bits in the third bin (thatis, the bits with program thresholds greater than α+Δ). In someembodiments, the sender may further obscure the partially-programmedbits by randomly inserting “0” and “1” bits according to a key maskgenerated using a password or other cryptographic value. The sender maythen provide the partially-programmed memory to the receiver. In someembodiments, the sender may also provide the key mask to the receiveralong with the partially-programmed memory, or may provide the key maskto the receiver before or after providing the partially-programmedmemory.

At block 612 (“Receiver reads programmed bit values”), which may followblock 610, the receiver in possession of the partially-programmed memorymay first use a read module (for example, the read module 106) to readthe data values of the partially-programmed memory bits. At this point,bits belonging to the first bin may read the digital value of “1”, bitsbelonging to the third bin may read “0”, and bits belonging to themiddle bin may mostly read “0”. If the receiver also possesses the bitbin map (as described above), then the receiver may use the bit bin mapand the initially-read values to determine whether the memory isactually the authentic partially-programmed memory or a fake. Forexample, if the bit bin map indicates that a particular bit belongs tothe first bin, but the value read from that bit in the memory is “0”,then the receiver may know that the memory is fake.

At block 614 (“Receiver performs partial program using 2Δ pulses to allbits and reads resulting values”), which may follow block 612, thereceiver may use a program module such as the program module 108 toperform a blind partial program operation by applying 2Δ program pulsesto each of the bits in the memory, as described above, and record theresulting bit values. After the blind partial program operation, thebits in the middle bin selected to store the digital “1” data values(for example, based on the key mask) may change values from “0” to “1”to the reader. However, the bits in the middle bin selected to store “0”data values, as well as the bits in the third bin, may not have receivedsufficient program pulses to change the digital values. In someembodiments, the receiver is not able to distinguish between the bits inthe middle bin storing “0” data values and the bits in the third bin ifthe receiver does not have the bin map for the received memory.

At block 616 (“Receiver has bit bin map?”), which may follow block 614,the receiver may determine whether it possesses a bin map for thereceived memory. If not, then the receiver may not yet be able todistinguish the bits in the middle bin that hold “0” data values frombits in the third bin that do not hold data values. Accordingly, atblock 618 (“Receiver performs partial program using α−Δ pulses to allbits and reads resulting values”), which may follow block 616, thereceiver may use the program module to perform an additional blindpartial program by applying α−Δ program pulses to each bit in the memoryand then record the resulting bit values. At this point, any bits thatchange value may be the “0” bits in the middle bin, and any bits that donot change value may be bits belonging to the third bin. At this point,the receiver may be able to determine the complete bit bin map andretrieve the data from the memory. On the other hand, if at block 616the receiver determines that it does possess a bin map for the receivedmemory, then the receiver may use the bin map to distinguish “0” bits inthe middle bin from bits in the third bin after block 612, and may notneed to perform block 618.

In either case, at block 620 (“Receiver derives intended data from readvalues, bit bin map, and optional password-derived code”), which mayfollow block 616 and/or block 618, the receiver may derive the intendeddata using the values read in blocks 612, 614, 618, the bit bin map,and/or the optional password-derived code if block 606 was performed.

At block 622 (“Receiver performs complete program and erase ofpage/block”), which may follow block 620, the receiver may use theprogram module to perform a complete program and erase of the memorystoring the data in order to prepare the memory for further use.

FIG. 7 is an illustration of a second example process 700 forprogramming and recovering data on a memory device having PUFs usingpartial programming, arranged in accordance with at least someembodiments described herein. Process 700 may include one or moreoperations, functions, or actions as illustrated by one or more ofblocks 702-716. Although some of the blocks in process 700 areillustrated in a sequential order, these blocks may also be performed inparallel and/or in a different order than those described herein. Also,the various blocks may be combined into fewer blocks, divided intoadditional blocks, and/or eliminated based upon the particularimplementation. Additional blocks representing other operations,functions, or actions may be provided.

According to process 700, programming and recovering data on a memorydevice having PUFs using partial programming may begin at block 702(“Sender performs complete erase of page/block”), which may be similarto block 602 in process 600. At block 704 (“Sender measures programthresholds for bits in page/block and assigns to three bins”), which mayfollow block 702 and may be similar to block 604 in process 600, thesender may measure the program thresholds for each bit in the memoryportion erased at block 702 and assign each bit to one of three bins.

At block 706 (“Sender computes data-to-write from intended data andpassword-derived code”), which may follow block 704, the sender may usea password-derived code to compute the data to be written on the memory,similar to block 606. In some embodiments, the sender may compute thedata by combining an intended data with the password-derived code usinga bitwise XOR or XNOR function.

At block 708 (“Sender programs data-to-write to specific bits using α−Δpulses for ‘1’ bits, no pulses for ‘0’ bits in lowest bin, and α−3Δpulses for ‘0’ bits in middle bin”), which may follow block 706, thesender may use the program module to apply program pulses to bits basedon the data-to-write. For example, the sender may first use a key maskor some other method to select the bits onto which the data is to bepartially programmed. In some embodiments, bits across two or more ofthe three bins may be selected for the data. The sender may partiallyprogram the selected bits with the data by applying α−Δ program pulsesto bits in the selected bits that are to store digital “1” values. Thesender may then partially program bits in the selected bits that (a) areto store “0” data values and (b) are in the lowest bin (that is, thebits with write thresholds less than α−Δ) with no program pulses, andmay then partially program bits in the selected bits that (a) are tostore “0” and (b) are in the middle bin with α−3Δ program pulses. Thesender may then provide the partially-programmed memory to the receiver.

At block 710 (“Receiver reads programmed bit values”), which may followblock 708, the reader in possession of the partially-programmed memorymay use a read module (for example, the read module 106) to read andrecord the data values of the partially-programmed memory bits. At block712 (“Receiver performs partial program using Δ pulses to bits in lowestbin and 2Δ pulses to bits in middle bin and reads resulting values”),which may follow block 710, the receiver, who is also in possession ofboth the bit bin map and the password-derived code, performs a partialprogram of the memory using a program module (for example, the programmodule 108). First, the receiver may use the bit bin map to identifybits in the lowest bin, bits in the middle bin, and bits in the highestbin. Second, the receiver may use the program module to apply Δ pulsesto each bit in the lowest bin and 2Δ pulses to each bit in the middlebin. The reader may then read and record the data values of the bits inthe lowest and middle bins.

At block 714 (“Receiver derives intended data from read values andpassword-derived code”), which may follow block 712, the receiver mayuse the password-derived code and the data values read in blocks 710 and712 to derive the intended data. For example, the receiver may firstderive the data-to-write based on the bit bin map and the data valuesread in blocks 710 and 712. Bits in the lowest bin that store “1” datavalues may already read “1” at block 710, and bits in the lowest binthat store “O” data values may read “0” at block 714. Bits in the middlebin that store “1” data values may already read “1” at block 710, andbits in the middle bin that store “0” data values may read “0” at block710 and “1” at block 714. Bits in the highest bin may be used todetermine whether the memory is actually the authenticpartially-programmed memory or a fake, as described above in process600.

At block 716 (“Receiver performs complete program and erase ofpage/block”), which may follow block 714, the receiver may use theprogram module to perform a complete program and erase of the memorystoring the data in order to prepare the memory for further use.

In process 700, an attacker with no prior knowledge of the bit bin mapmay not be able to distinguish between bits in different bins. As aresult, the attacker may only be able to apply the same number ofprogram pulses to every bit. If the number of program pulses applied istoo few, the data in the middle bin may be wrong. On the other hand, ifthe number of write pulses applied is too many, the data in the lowestbin may be wrong. Moreover, progressive application of program pulsesmay confuse the data readout between “0” and “l” values. Any attempts bythe attacker to obtain the bit bin map from the physical memory mayresult in destroying the data.

Example embodiments discussed above may provide some data securityagainst attackers, because an attacker must have the physical memory,the password or key mask used to partially program the data onto thememory, and possibly also the bit bin map. Merely copying the digitalvalues (that is, “0” or “1”) of the memory bits may be useless, becausethe application of specific program pulses may be needed to recover theintended data. Merely having the physical memory without knowledge ofthe password/key mask or the bit bin mask may also be useless to anattacker, because the attacker may not know how to apply the specificprogram pulses to recover the intended data. It may be nearly impossiblefor the attacker due to computational cost to try to recover the datawithout the password or key mask.

The example embodiments discussed above may also provide memory tamperdetection. If a receiver has the bit bin map for a physical memory, thereceiver may be able to determine whether the bits in the physicalmemory actually correspond to the bit bin map. The receiver may also beable to determine whether bits that should not have changed values havein fact changed values (for example, due to attempted partialprogramming by an attacker). In some embodiments, additional securitymay be provided by preventing any reader of the memory, including thereceiver, from being able to erase the physical memory. Thus, thereading operation may be performed only one time, and the data may beguaranteed to be destroyed by having every bit read as digital “1”.

Secure data storage based on physically unclonable functions and partialprogram operations as described herein may be modified in several ways.In one embodiment, multiple copies of an intended data, each writteninto different memories or memory portions, may be provided to avoiddata loss due to accidental use of the wrong password. In thisembodiment, the apparent data content for the intended data may differacross the different memories due to the physical differences betweenthe different memories. In other embodiments, error correction codes maybe employed to assist in data retrieval and to account for age-based bitdecay or fluctuation. In some embodiments, partial erase operations maybe used to encode data into physical memory in addition to or instead ofpartial program operations. If memory bits are not categorized intothree bins, the Hamming distance associated with different encodings maybe calculated to provide sufficient separation between an authenticreader from an attacker by correlation functions.

FIG. 8 is an illustration of a general purpose computing device, whichmay be used to provide secure data storage based on physicallyunclonable functions, arranged in accordance with at least someembodiments described herein.

For example, the computing device 800 may be used to write or read datausing physically unclonable functions and partial program operations asdescribed herein. In an example basic configuration 802, the computingdevice 800 may include one or more processors 804 and a system memory806. A memory bus 808 may be used to communicate between the processor804 and the system memory 806. The basic configuration 802 isillustrated in FIG. 8 by those components within the inner dashed line.

Depending on the desired configuration, the processor 804 may be of anytype, including but not limited to a microprocessor (μP), amicrocontroller (μC), a digital signal processor (DSP), or anycombination thereof. The processor 804 may include one more levels ofcaching, such as a cache memory 812, a processor core 814, and registers816. The example processor core 814 may include an arithmetic logic unit(ALU), a floating point unit (FPU), a digital signal processing core(DSP Core), or any combination thereof. An example memory controller 818may also be used with the processor 804, or in some implementations thememory controller 818 may be an internal part of the processor 804.

Depending on the desired configuration, the system memory 806 may be ofany type including but not limited to volatile memory (such as RAM),non-volatile memory (such as ROM, flash memory, etc.) or any combinationthereof. The system memory 806 may include an operating system 820, aphysically unclonable function (PUF) data module 822, and program data824. The PUF data module 822 may include a PUF encoding module 826 and aPUF decoding module 828 to implement secure data storage and transferusing PUFs as described herein. The program data 824 may include, amongother data, bit bin map data 831 or the like, as described herein.

The computing device 800 may have additional features or functionality,and additional interfaces to facilitate communications between the basicconfiguration 802 and any desired devices and interfaces. For example, abus/interface controller 830 may be used to facilitate communicationsbetween the basic configuration 802 and one or more data storage devices832 via a storage interface bus 834. The data storage devices 832 may beone or more removable storage devices 836, one or more non-removablestorage devices 838, or a combination thereof. Examples of the removablestorage and the non-removable storage devices include magnetic diskdevices such as flexible disk drives and hard-disk drives (HDD), opticaldisk drives such as compact disk (CD) drives or digital versatile disk(DVD) drives, solid state drives (SSD), and tape drives to name a few.Example computer storage media may include volatile and nonvolatile,removable and non-removable media implemented in any method ortechnology for storage of information, such as computer readableinstructions, data structures, program modules, or other data.

The system memory 806, the removable storage devices 836 and thenon-removable storage devices 838 are examples of computer storagemedia. Computer storage media includes, but is not limited to, RAM, ROM,EEPROM, flash memory or other memory technology, CD-ROM, digitalversatile disks (DVD), solid state drives, or other optical storage,magnetic cassettes, magnetic tape, magnetic disk storage or othermagnetic storage devices, or any other medium which may be used to storethe desired information and which may be accessed by the computingdevice 800. Any such computer storage media may be part of the computingdevice 800.

The computing device 800 may also include an interface bus 840 forfacilitating communication from various interface devices (e.g., one ormore output devices 842, one or more peripheral interfaces 844, and oneor more communication devices 866) to the basic configuration 802 viathe bus/interface controller 830. Some of the example output devices 842include a graphics processing unit 848 and an audio processing unit 850,which may be configured to communicate to various external devices suchas a display or speakers via one or more A/V ports 852. One or moreexample peripheral interfaces 844 may include a serial interfacecontroller 854 or a parallel interface controller 856, which may beconfigured to communicate with external devices such as input devices(e.g., keyboard, mouse, pen, voice input device, touch input device,etc.) or other peripheral devices (e.g., printer, scanner, etc.) via oneor more I/O ports 858. An example communication device 866 includes anetwork controller 860, which may be arranged to facilitatecommunications with one or more other computing devices 862 over anetwork communication link via one or more communication ports 864. Theone or more other computing devices 862 may include servers at adatacenter, customer equipment, and comparable devices.

The network communication link may be one example of a communicationmedia. Communication media may be embodied by computer readableinstructions, data structures, program modules, or other data in amodulated data signal, such as a carrier wave or other transportmechanism, and may include any information delivery media. A “modulateddata signal” may be a signal that has one or more of its characteristicsset or changed in such a manner as to encode information in the signal.By way of example, and not limitation, communication media may includewired media such as a wired network or direct-wired connection, andwireless media such as acoustic, radio frequency (RF), microwave,infrared (IR) and other wireless media. The term computer readable mediaas used herein may include both storage media and communication media.

The computing device 800 may be implemented as a part of a generalpurpose or specialized server, mainframe, or similar computer thatincludes any of the above functions. The computing device 800 may alsobe implemented as a personal computer including both laptop computer andnon-laptop computer configurations.

FIG. 9 is a flow diagram illustrating an example method for providingsecure data storage based on physically unclonable functions that may beperformed by a computing device such as the computing device in FIG. 8,arranged in accordance with at least some embodiments described herein.

Example methods may include one or more operations, functions or actionsas illustrated by one or more of blocks 922, 924, 926, 928, and/or 928,and may in some embodiments be performed by a computing device such asthe computing device 900 in FIG. 9. The operations described in theblocks 922-928 may also be performed in response to execution (by one ormore processors) of computer-executable instructions stored in acomputer-readable medium such as a non-transitory computer-readablemedium 920 of a computing device 910. Computing device 910 may beembodied by computing device 800 of FIG. 8.

An example process to provide secure data storage based on physicallyunclonable functions may begin with block 922, “SENDER MEASURES PUFCHARACTERISTICS OF MEMORY PAGE/BLOCK AND GROUPS BITS INTO BINS”, where asender who wishes to send data to a receiver may measure physicallyunclonable function (PUF) characteristics associated with bits in aphysical memory page, block, or section, and use the measuredcharacteristics to group the bits. For example, the sender may measure aprogram threshold average and a program threshold variation associatedwith the bits and use the measured average and variation to group thebits into three bins, as described above.

Block 922 may be followed by block 924, “SENDER WRITES DATA TO SPECIFICBITS IN ONE OR MORE BINS USING PARTIAL PROGRAMMING BASED ON PUFCHARACTERISTICS”, where the sender may select a set of bits from one ormore bins and partially program data to the selected bits. In someembodiments, the sender may select the set of bits using a key mask orfrom multiple bins, as described above. The sender may partially programthe data to the selected bits by applying write pulses based on the PUFcharacteristics (for example, the program threshold average and theprogram threshold variation) measured in block 922.

Block 924 may be followed by block 926, “SENDER PROVIDES MEMORY TORECEIVER”, where the sender provides the partially-programmed physicalmemory to a receiver.

Block 926 may be followed by block 928, “RECEIVER PERFORMS PARTIALPROGRAMMING ON BITS BASED ON PUF CHARACTERISTICS AND/OR BIT BIN MAP”,where the receiver partially programs the bits in the received physicalmemory, as described above. In some embodiments, the receiver may knowthe PUF characteristics of the physical memory as well as a bit bin maprelating the bits in the physical memory to their corresponding bin. Thereceiver may then use this information to select the bits to partiallyprogram as well as the number of write pulses to use for the partialprogramming, and may then partially program the selected bits, asdescribed above.

Block 928 may be followed by block 930, “RECEIVER READS RESULTING BITVALUES AND RECOVERS DATA”, where the receiver may read the bit datavalues on the memory before and/or after partial programming and use theread data to recover the actual data, as described above. In someembodiments, the receiver may use a password-derived code to recover thebit data values on the memory, as described above.

FIG. 10 is an illustration of a block diagram of an example computerprogram product, arranged in accordance with at least some embodimentsdescribed herein.

In some examples, as shown in FIG. 10, a computer program product 1000may include a signal bearing medium 1002 that may also include one ormore machine readable instructions 1004 that, in response to executionby, for example, a processor may provide the functionality and featuresdescribed herein. Thus, for example, referring to the processor 804 inFIG. 8, the PUF data module 822 may undertake one or more of the tasksshown in FIG. 10 in response to the instructions 1004 conveyed to theprocessor 804 by the signal bearing medium 1002 to perform actionsassociated data storage and transfer using PUFs as described herein.Some of those instructions may include, for example, instructions tomeasure PUF characteristics of a memory page/block and group bits intobins, write data to specific bits in one or more bins using partialprogramming based on PUF characteristics, provide the memory to areceiver, perform partial programming on bits based on PUFcharacteristics and/or a bin bit map, and/or read the resulting bitvalues and recover the data, according to some embodiments describedherein.

In some implementations, the signal bearing medium 1002 depicted in FIG.10 may encompass computer-readable medium 1006, such as, but not limitedto, a hard disk drive (HDD), a solid state drive (SSD), a Compact Disc(CD), a Digital Versatile Disk (DVD), a digital tape, memory, etc. Insome implementations, the signal bearing medium 1002 may encompassrecordable medium 1008, such as, but not limited to, memory, read/write(R/W) CDs, R/W DVDs, etc. In some implementations, the signal bearingmedium 1002 may encompass communications medium 1010, such as, but notlimited to, a digital and/or an analog communication medium (e.g., afiber optic cable, a waveguide, a wired communications link, a wirelesscommunication link, etc.). Thus, for example, the computer programproduct 1000 may be conveyed to one or more modules of the processor 704by an RF signal bearing medium, where the signal bearing medium 1002 isconveyed by the wireless communications medium 1010 (e.g., a wirelesscommunications medium conforming with the IEEE 802.11 standard).

According to some examples, a method is provided to write data on anonvolatile memory using a physically unclonable function. The methodmay include determining, for multiple memory bits on the nonvolatilememory, a program threshold average and a program threshold variation.The method may further include deriving, based on the program thresholdaverage and the program threshold variation, a first bin threshold and asecond bin threshold, and grouping the bits into at least a first bitgroup, a second bit group, and a third bit group, based on at least thefirst bin threshold and the second bin threshold. The method may furtherinclude determining, based on at least the grouping of the bits, a setof bits to which the data is to be written, and performing a partialprogram of the data to the set of bits based on the program thresholdaverage and the program threshold variation.

According to some embodiments, the program threshold may represent anumber of program pulses to modify a bit in the multiple bits from afirst value to a second value. Grouping the multiple bits may includedetermining a respective program threshold for each bit in the multiplebits and assigning each bit in the multiple bits having a respectiveprogram threshold less than the first bin threshold to the first bitgroup. Grouping the multiple bits may further include assigning each bitin the multiple bits having a respective program threshold greater thanthe first bin threshold and less than the second bin threshold to thesecond bit group and assigning each bit in the multiple bits having arespective program threshold greater than the second bin threshold tothe third bit group.

According to other embodiments, grouping the multiple bits may furtherinclude generating a bit bin map based on the grouping. The first binthreshold may be derived by subtracting the program threshold variationfrom the program threshold average and the second bin threshold may bederived by adding the program threshold variation to the programthreshold average. Determining the set of bits to which the data is tobe written may further include selecting the set of bits from the secondbit group. Determining the set of bits to which the data is to bewritten may be based on a key mask and/or the grouping of the pluralityof bits. The method may further include deriving the data to be writtenfrom a password-derived value and an intended data value. Deriving thedata to be written may include inserting random bit values intopositions of an intended data indicated by a key mask.

According to further embodiments, performing the partial program of thedata may further include writing a bit value of “1” in the data to bitsin the set of bits using a number of program pulses equal to the firstbin threshold and writing a bit value of “0” in the data to bits in theset of bits using zero program pulses. Performing the partial program ofthe data may further include writing a bit value of “1” in the data tobits in the set of bits using a number of program pulses equal to thefirst bin threshold, writing a bit value of “0” in the data to bits inthe set of bits belonging to the second bit group using zero programpulses, and writing a bit value of “0” in the data to bits in the set ofbits belonging to the third bit group using a number of program pulsesequal to a third threshold.

According to other examples, an encoding module is provided to writedata on a nonvolatile memory using a physically unclonable function. Theencoding module may include an interface configured to couple tomultiple memory bits on the nonvolatile memory and a processor block.The processor block may be configured to determine, for the multiplememory bits, a program threshold average and a program thresholdvariation. The processor block may be further configured to derive, fromthe program threshold average and the program threshold variation, afirst bin threshold and a second bin threshold, and group the multiplebits into at least a first bit group, a second bit group, and a thirdbit group, based on at least the first bin threshold and the second binthreshold. The processor block may be further configured to determine,based on at least the grouping of the bits and a key mask, a set of bitsto which the data is to be written, and performing a partial program ofthe data to the set of bits based on the write threshold average and theprogram threshold variation.

According to some embodiments, the processor block may be furtherconfigured to group the multiple bits by determining a respectiveprogram threshold for each bit in the multiple bits and assigning eachbit in the multiple bits having a respective program threshold less thanthe first bin threshold to the first bit group. The processor block maybe further configured to group the multiple bits by assigning each bitin the multiple bits having a respective program threshold greater thanthe first bin threshold and less than the second bin threshold to thesecond bit group and by assigning each bit in the multiple bits having arespective program threshold greater than the second bin threshold tothe third bit group. The processor block may be configured to group themultiple bits by generating a bit bin map based on the grouping.

According to other embodiments, the processor block is configured toderive the first bin threshold by subtracting the program thresholdvariation from the program threshold average and derive the second binthreshold by adding the program threshold variation to the programthreshold average. The processor block may be configured to determinethe set of bits to which the data is to be written by selecting the setof bits from the second bit group. The processor block may be furtherconfigured to derive the data to be written from a password-derivedvalue and an intended data value. The processor block may be furtherconfigured to derive the data to be written by inserting random bitvalues into positions of an intended data indicated by the key mask toform the data to be written.

According to further embodiments, the processor block may be configuredto perform the partial program of the data by writing a bit value of “1”in the data to bits in the set of bits using a number of program pulsesequal to the first bin threshold and writing a bit value of “0” in thedata to bits in the set of bits using zero program pulses. The processorblock may be configured to perform the partial program of the data bywriting a bit value of “1” in the data to bits in the set of bits usinga number of program pulses equal to the first bin threshold, writing abit value of “0” in the data to bits in the set of bits belonging to thesecond bit group using zero program pulses, and writing a bit value of“0” in the data to bits in the set of bits belonging to the third bitgroup using a number of program pulses equal to a third threshold.

According to further examples, a method is provided to read data from anonvolatile memory using a physically unclonable function. The methodmay include applying at least one program pulse to at least one bit inmultiple memory bits in the nonvolatile memory based on a programthreshold average, a program threshold variation, and/or a bit groupcharacterization associated with the at least one bit. The method mayfurther include reading a resulting state of the multiple memory bitsand deriving a final data based on the resulting state and another datavalue.

According to some embodiments, the method may include reading an initialstate for the multiple memory bits, and deriving the final data mayinclude deriving the final data based on at least the resulting stateand the initial state. The method may include deriving a first programparameter from the program threshold average and the program thresholdvariation, and applying the at least one program pulse may includeapplying a number of program pulses equal to the first program parameterto every bit in the multiple memory bits. The method may further includederiving a second program parameter from the program threshold averageand the program threshold variation, again applying a number of programpulses equal to the second program parameter to every bit in themultiple memory bits, and reading another state of the multiple memorybits, where deriving the final data includes deriving the final databased on at least the resulting state, the initial state, and the otherstate.

According to other embodiments, the method may include grouping themultiple memory bits into a first bit group, a second bit group, and athird bit group based on the bit group characterization and deriving afirst program parameter and a third program parameter from the programthreshold average and the program threshold variation. Applying the atleast one program pulse may further include applying a number of programpulses equal to the first program parameter to bits in the multiplememory bits in the second bit group and applying a number of programpulses equal to the third program parameter to bits in the multiplememory bits in the first bit group. The other data value may be apassword-derived value and/or a key mask. The method may further includeauthenticating the multiple memory bits based on a bit bin map and/orrecovering a bit bin map based on the resulting state.

According to yet further examples, a decoding module is provided to readdata from a nonvolatile memory using a physically unclonable function.The decoding module may include an interface configured to couple tomultiple memory bits in the nonvolatile memory and a processor block.The processor block may be configured to apply at least one programpulse to one or more bits in the multiple memory bits based on a programthreshold average, a program threshold variation, and/or a bit groupcharacterization associated with the bit(s), where the program thresholdmay represent a number of program pulses to modify a bit in the memorybits from a first value to a second value. The processor block may befurther configured to read a resulting state of the multiple memory bitsand derive a final data based on the resulting state and another datavalue.

According to some embodiments, the processor block may be furtherconfigured to read an initial state for the multiple memory bits andderive the final data based on at least the resulting state and theinitial state. The processor block may be further configured to derive afirst program parameter from the program threshold average and theprogram threshold variation and apply the at least one program pulse byapplying a number of program pulses equal to the first program parameterto every bit in the multiple memory bits. The processor block may befurther configured to derive a second program parameter from the programthreshold average and the program threshold variation, again apply anumber of program pulses equal to the second program parameter to everybit in the multiple memory bits, read another state of the multiplememory bits, and derive the final data based on at least the resultingstate, the initial state, and the other state.

According to other embodiments, the processor block may be furtherconfigured to group the multiple memory bits into a first bit group, asecond bit group, and a third bit group based on the bit groupcharacterization and derive a first program parameter and a thirdprogram parameter from the program threshold average and the programthreshold variation. The processor block may be further configured toapply at least one program pulse by applying a number of program pulsesequal to the first program parameter to bits in the multiple memory bitsin the second bit group and applying a number of program pulses equal tothe third program parameter to bits in the multiple memory bits in thefirst bit group. The other data value may be a password-derived value.The processor block may be further configured to authenticate themultiple memory bits based on a bit bin map and/or recover a bit bin mapbased on the resulting state.

Various embodiments may be implemented in hardware, software, orcombination of both hardware and software (or other computer-readableinstructions stored on a non-transitory computer-readable storage mediumand executable by one or more processors); the use of hardware orsoftware is generally (but not always, in that in certain contexts thechoice between hardware and software may become significant) a designchoice representing cost vs. efficiency tradeoffs. There are variousvehicles by which processes and/or systems and/or other technologiesdescribed herein may be effected (e.g., hardware, software, and/orfirmware), and the preferred vehicle will vary with the context in whichthe processes and/or systems and/or other technologies are deployed. Forexample, if an implementer determines that speed and accuracy areparamount, the implementer may opt for a mainly hardware and/or firmwarevehicle; if flexibility is paramount, the implementer may opt for amainly software implementation; or, yet again alternatively, theimplementer may opt for some combination of hardware, software, and/orfirmware.

The foregoing detailed description has set forth various embodiments ofthe devices and/or processes via the use of block diagrams, flowcharts,and/or examples. Insofar as such block diagrams, flowcharts, and/orexamples contain one or more functions and/or operations, each functionand/or operation within such block diagrams, flowcharts, or examples maybe implemented, individually and/or collectively, by a wide range ofhardware, software, firmware, or virtually any combination thereof. Inone embodiment, several portions of the subject matter described hereinmay be implemented via Application Specific Integrated Circuits (ASICs),Field Programmable Gate Arrays (FPGAs), digital signal processors(DSPs), or other integrated formats. However, some aspects of theembodiments disclosed herein, in whole or in part, may be equivalentlyimplemented in integrated circuits, as one or more computer programsexecuting on one or more computers (e.g., as one or more programsexecuting on one or more computer systems), as one or more programsexecuting on one or more processors (e.g., as one or more programsexecuting on one or more microprocessors), as firmware, or as virtuallyany combination thereof, and designing the circuitry and/or writing thecode for the software and/or firmware are possible in light of thisdisclosure.

The present disclosure is not to be limited in terms of the particularembodiments described in this application, which are intended asillustrations of various aspects. Many modifications and variations canbe made without departing from its spirit and scope. Functionallyequivalent methods and apparatuses within the scope of the disclosure,in addition to those enumerated herein, are possible from the foregoingdescriptions. Such modifications and variations are intended to fallwithin the scope of the appended claims. The present disclosure is to belimited only by the terms of the appended claims, along with the fullscope of equivalents to which such claims are entitled. Also, theterminology used herein is for the purpose of describing particularembodiments only, and is not intended to be limiting.

In addition, the mechanisms of the subject matter described herein arecapable of being distributed as a program product in a variety of forms,and that an illustrative embodiment of the subject matter describedherein applies regardless of the particular type of signal bearingmedium used to actually carry out the distribution. Examples of a signalbearing medium include, but are not limited to, the following: arecordable type medium such as a floppy disk, a hard disk drive (HDD), aCompact Disc (CD), a Digital Versatile Disk (DVD), a digital tape, acomputer memory, a solid state drive, etc.; and a transmission typemedium such as a digital and/or an analog communication medium (e.g., afiber optic cable, a waveguide, a wired communications link, a wirelesscommunication link, etc.).

Those skilled in the art will recognize that it is common within the artto describe devices and/or processes in the fashion set forth herein,and thereafter use engineering practices to integrate such describeddevices and/or processes into data processing systems. That is, at leasta portion of the devices and/or processes described herein may beintegrated into a data processing system via a reasonable amount ofexperimentation. A data processing system may include one or more of asystem unit housing, a video display device, a memory such as volatileand non-volatile memory, processors such as microprocessors and digitalsignal processors, computational entities such as operating systems,drivers, graphical user interfaces, and applications programs, one ormore interaction devices, such as a touch pad or screen, and/or controlsystems including feedback loops and control motors (e.g., feedback forsensing position and/or velocity of gantry systems; control motors tomove and/or adjust components and/or quantities).

A data processing system may be implemented utilizing any suitablecommercially available components, such as those found in datacomputing/communication and/or network computing/communication systems.The herein described subject matter sometimes illustrates differentcomponents contained within, or connected with, different othercomponents. Such depicted architectures are merely exemplary, and infact many other architectures may be implemented which achieve the samefunctionality. In a conceptual sense, any arrangement of components toachieve the same functionality is effectively “associated” such that thedesired functionality is achieved. Hence, any two components hereincombined to achieve a particular functionality may be seen as“associated with” each other such that the desired functionality isachieved, irrespective of architectures or intermediate components.Likewise, any two components so associated may also be viewed as being“operably connected”, or “operably coupled”, to each other to achievethe desired functionality, and any two components capable of being soassociated may also be viewed as being “operably couplable”, to eachother to achieve the desired functionality. Specific examples ofoperably couplable include but are not limited to physically connectableand/or physically interacting components and/or wirelessly interactableand/or wirelessly interacting components and/or logically interactingand/or logically interactable components.

With respect to the use of substantially any plural and/or singularterms herein, those having skill in the art can translate from theplural to the singular and/or from the singular to the plural as isappropriate to the context and/or application. The varioussingular/plural permutations may be expressly set forth herein for sakeof clarity.

It will be understood by those within the art that, in general, termsused herein, and especially in the appended claims (e.g., bodies of theappended claims) are generally intended as “open” terms (e.g., the term“including” should be interpreted as “including but not limited to,” theterm “having” should be interpreted as “having at least,” the term“includes” should be interpreted as “includes but is not limited to,”etc.). It will be further understood by those within the art that if aspecific number of an introduced claim recitation is intended, such anintent will be explicitly recited in the claim, and in the absence ofsuch recitation no such intent is present. For example, as an aid tounderstanding, the following appended claims may contain usage of theintroductory phrases “at least one” and “one or more” to introduce claimrecitations. However, the use of such phrases should not be construed toimply that the introduction of a claim recitation by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim recitation to embodiments containing only one suchrecitation, even when the same claim includes the introductory phrases“one or more” or “at least one” and indefinite articles such as “a” or“an” (e.g., “a” and/or “an” should be interpreted to mean “at least one”or “one or more”); the same holds true for the use of definite articlesused to introduce claim recitations. In addition, even if a specificnumber of an introduced claim recitation is explicitly recited, thoseskilled in the art will recognize that such recitation should beinterpreted to mean at least the recited number (e.g., the barerecitation of“two recitations,” without other modifiers, means at leasttwo recitations, or two or more recitations).

Furthermore, in those instances where a convention analogous to “atleast one of A, B, and C, etc.” is used, in general such a constructionis intended in the sense one having skill in the art would understandthe convention (e.g., “a system having at least one of A, B, and C”would include but not be limited to systems that have A alone, B alone,C alone, A and B together, A and C together, B and C together, and/or A,B, and C together, etc.). It will be further understood by those withinthe art that virtually any disjunctive word and/or phrase presenting twoor more alternative terms, whether in the description, claims, ordrawings, should be understood to contemplate the possibilities ofincluding one of the terms, either of the terms, or both terms. Forexample, the phrase “A or B” will be understood to include thepossibilities of “A” or “B” or “A and B.”

As will be understood by one skilled in the art, for any and allpurposes, such as in terms of providing a written description, allranges disclosed herein also encompass any and all possible subrangesand combinations of subranges thereof. Any listed range can be easilyrecognized as sufficiently describing and enabling the same range beingbroken down into at least equal halves, thirds, quarters, fifths,tenths, etc. As a non-limiting example, each range discussed herein canbe readily broken down into a lower third, middle third and upper third,etc. As will also be understood by one skilled in the art all languagesuch as “up to,” “at least,” “greater than,” “less than,” and the likeinclude the number recited and refer to ranges which can be subsequentlybroken down into subranges as discussed above. Finally, as will beunderstood by one skilled in the art, a range includes each individualmember. Thus, for example, a group having 1-3 cells refers to groupshaving 1, 2, or 3 cells. Similarly, a group having 1-5 cells refers togroups having 1, 2, 3, 4, or 5 cells, and so forth.

While various aspects and embodiments have been disclosed herein, otheraspects and embodiments are possible. The various aspects andembodiments disclosed herein are for purposes of illustration and arenot intended to be limiting, with the true scope and spirit beingindicated by the following claims.

What is claimed is:
 1. A method to read data from a nonvolatile memoryusing a physically unclonable function, the method comprising: applyingat least one program pulse to at least one bit in a plurality of memorybits in the nonvolatile memory based on at least one of a programthreshold average, a program threshold variation, and a bit groupcharacterization associated with the at least one bit; reading aresulting state of the plurality of memory bits; and deriving a finaldata based on the resulting state.
 2. The method of claim 1, furthercomprising reading an initial state for the plurality of memory bits,and wherein deriving the final data comprises deriving the final databased on at least the resulting state and the initial state.
 3. Themethod of claim 2, further comprising deriving a first program parameterfrom the program threshold average and the program threshold variation,and wherein applying the at least one program pulse comprises applying anumber of program pulses equal to the first program parameter to everybit in the plurality of memory bits.
 4. The method of claim 3, furthercomprising: deriving a second program parameter from the programthreshold average and the program threshold variation; applying a numberof program pulses equal to the second program parameter to every bit inthe plurality of memory bits; and reading another state of the pluralityof memory bits, wherein deriving the final data comprises deriving thefinal data based on at least the resulting state, the initial state, andthe other state.
 5. The method of claim 1, further comprising: grouping,based on the bit group characterization, the plurality of memory bitsinto a first bit group, a second bit group, and a third bit group; andderiving, from the program threshold average and the program thresholdvariation, a first program parameter and a third program parameter,wherein: applying the at least one program pulse comprises: applying anumber of program pulses equal to the first program parameter to bits inthe plurality of memory bits in the second bit group; and applying anumber of program pulses equal to the third program parameter to bits inthe plurality of memory bits in the first bit group.
 6. An apparatus,comprising: a decoder configured to read data from a nonvolatile memoryby use of a physically unclonable function; an interface configured tocouple to a plurality of memory bits in the nonvolatile memory; and aprocessor coupled to the interface and the decoder, the processorconfigured to operate with the interface and the decoder to: apply atleast one program pulse to at least one bit in the plurality of memorybits based on at least one of a program threshold average, a programthreshold variation, and a bit group characterization associated withthe at least one bit, wherein the program threshold represents a numberof program pulses to modify a bit in the plurality of memory bits from afirst value to a second value; read a resulting state of the pluralityof memory bits; and derive a final data based on the resulting state. 7.The apparatus of claim 6, wherein the processor is configured to: readan initial state for the plurality of memory bits; and derive the finaldata based on at least the resulting state and the initial state.
 8. Theapparatus of claim 7, wherein the processor is configured to: derive afirst program parameter from the program threshold average and theprogram threshold variation; and apply the at least one program pulse byapplication of a number of program pulses equal to the first programparameter to every bit in the plurality of memory bits.
 9. The apparatusof claim 8, wherein the processor is configured to: derive a secondprogram parameter from the program threshold average and the programthreshold variation; apply a number of program pulses equal to thesecond program parameter to every bit in the plurality of memory bits;read another state of the plurality of memory bits; and derive the finaldata based on at least the resulting state, the initial state, and theother state.
 10. The apparatus of claim 6, wherein the processor isconfigured to: group, based on the bit group characterization, theplurality of memory bits into a first bit group, a second bit group, anda third bit group; derive, from the program threshold average and theprogram threshold variation, a first program parameter and a thirdprogram parameter, and apply the at least one program pulse by:application of a number of program pulses equal to the first programparameter to bits in the plurality of memory bits in the second bitgroup; and application of a number of program pulses equal to the thirdprogram parameter to bits in the plurality of memory bits in the firstbit group.
 11. A non-transitory computer-readable storage medium havingstored thereon computer-executable instructions that, in response toexecution, cause a processor to perform or control performance ofoperations to: apply at least one program pulse to at least one bit in aplurality of memory bits in a nonvolatile memory based on at least oneof a program threshold average, a program threshold variation, and a bitgroup characterization associated with the at least one bit, wherein theprogram threshold represents a number of program pulses to modify a bitin the plurality of memory bits from a first value to a second value;read a resulting state of the plurality of memory bits; and derive afinal data based on the resulting state.
 12. The non-transitorycomputer-readable storage medium of claim 11, wherein the executableinstructions, in response to execution, cause the processor to performor control performance of at least one operation to: read an initialstate for the plurality of memory bits; and derive the final data basedon at least the resulting state and the initial state.
 13. Thenon-transitory computer-readable storage medium of claim 12, wherein theexecutable instructions, in response to execution, cause the processorto perform or control performance of at least one operation to: derive afirst program parameter from the program threshold average and theprogram threshold variation; and apply the at least one program pulse byapplication of a number of program pulses equal to the first programparameter to every bit in the plurality of memory bits.
 14. Thenon-transitory computer-readable storage medium of claim 13, wherein theexecutable instructions, in response to execution, cause the processorto perform or control performance of at least one operation to: derive asecond program parameter from the program threshold average and theprogram threshold variation; apply a number of program pulses equal tothe second program parameter to every bit in the plurality of memorybits; read another state of the plurality of memory bits; and derive thefinal data based on at least the resulting state, the initial state, andthe other state.
 15. The non-transitory computer-readable storage mediumof claim 11, wherein the executable instructions, in response toexecution, cause the processor to perform or control performance of atleast one operation to: group, based on the bit group characterization,the plurality of memory bits into a first bit group, a second bit group,and a third bit group; derive, from the program threshold average andthe program threshold variation, a first program parameter and a thirdprogram parameter; and apply the at least one program pulse by:application of a number of program pulses equal to the first programparameter to bits in the plurality of memory bits in the second bitgroup; and application of a number of program pulses equal to the thirdprogram parameter to bits in the plurality of memory bits in the firstbit group.